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1 of 23 september 7, 2007 ? 2007 integrated device technology, inc. *notice: the information in this document is subject to change without notice advance information idt and the idt logo are registered trademarks of integrated device technology, inc. ? device overview the 89hpes4t4 is a member of idt?s precise? family of pci express switching solutions. the pes4t4 is a 4-lane, 4-port peripheral chip that performs pci express base switching. it provides connectivity and switching functions between a pci express upstream port and up to four downstream ports and supports switching between downstream ports. features high performance pci express switch ? four 2.5 gbps pci express lanes ? four switch ports ? x1 upstream port ? three x1 downstream ports ? low latency cut-through switch architecture ? support for max payload sizes up to 256 bytes ? one virtual channel ? eight traffic classes ? pci express base specification revision 1.1 compliant flexible architecture with nume rous configuration options ? automatic lane reversal on all ports ? automatic polarity inversion on all lanes ? ability to load device configuration from serial eeprom legacy support ? pci compatible intx emulation ? bus locking highly integrated solution ? requires no external components ? incorporates on-chip internal memory for packet buffering and queueing ? integrates four 2.5 gbps embedded serdes with 8b/10b encoder/decoder (no separate transceivers needed) reliability, availability, and serviceability (ras) features ? internal end-to-end parity protection on all tlps ensures data integrity even in systems that do not implement end-to-end crc (ecrc) ? supports ecrc and advanced error reporting ? supports pci express native hot-plug, hot-swap capable i/o ? compatible with hot-plug i/o expanders used on pc mother- boards power management ? utilizes advanced low-power design techniques to achieve low typical power consumption ? supports pci power management interface specification (pci- pm 1.2) ? unused serdes are disabled. ? supports advanced configuration and power interface speci- fication, revision 2.0 (acpi) supporting active link state testability and debug features ? built in pseudo-random bit stream (prbs) generator ? numerous serdes test modes ? ability to bypass link training and force any link into any mode ? provides statistics and performance counters block diagram figure 1 internal block diagram 4-port switch core / 4 pci express lanes frame buffer route table port arbitration scheduler serdes phy logical layer mux / demux transaction layer data link layer (port 0) (port 2) serdes phy logical layer mux / demux transaction layer data link layer serdes phy logical layer mux / demux transaction layer data link layer (port 3) (port 4) serdes phy logical layer transaction layer data link layer mux / demux 89hpes4t4 data sheet advance information* 4-lane 4-port pci express? switch
2 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information 5 general purpose input/output pins ? each pin may be individually configured as an input or output ? each pin may be individually configured as an interrupt input ? each pin has a selectable alternate function packaged in a 13mm x 13mm 144-ball bga with 1mm ball spacing product description utilizing standard pci express interconnect, the pes4t4 provides the most efficient fan-out solution for applications requiring x1 connectivity, low latency, and simple board layout with a minimum number of board la yers. each lane provides 2.5 gbps of bandwidth in both direct ions and is fully compliant with pci express base specification 1.1. the pes4t4 is based on a flexible and efficient layered architectu re. the pci express layer consists of serdes, physical, data link and transac- tion layers in compliance with pci express base specification re vision 1.1. the pes4t4 can operate either as a store and forwar d or cut-through switch and is designed to switch memory and i/o transactions. it supports eight traffic classes (tcs) and one virtual channel ( vc) with sophisticated resource management to allow efficient switching for applicati ons requiring additional narrow port connectivity and also some h igh-end connectivity. figure 2 i/o expansion application smbus interface the pes4t4 contains an smbus master interface. this master inte rface allows the default configurat ion register values of the pe s4t4 to be over- ridden following a reset with values programmed in an external seri al eeprom. the master interface is also used by an external hot-plug i/o expander. two pins make up the smbus master interface. thes e pins consist of an smbus clock pin and an smbus data pin. hot-plug interface the pes4t4 supports pci express hot-plug on each downstream port. to reduce the number of pins required on the device, the pes4 t4 utilizes an external i/o expander, such as that used on pc motherboards, c onnected to the smbus master interface. following reset and co nfiguration, when- ever the state of a hot-plug output needs to be modified, the pe s4t4 generates an smbus transaction to the i/o expander with th e new value of all of the outputs. whenever a hot-plug input changes, the i/o expander gener ates an interrupt which is received on the ioexpintn inpu t pin (alternate function of gpio) of the pes4t4. in response to an i/o expander interrupt, the pes4t4 generates an smbus transaction to read th e state of all of the hot-plug inputs from the i/o expander. memory memory memory processor memory north bridge pes4t4 processor x1 x1 ge x1 south bridge ge 1394 lom lom x1
3 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information general purpose input/output the pes4t4 provides 5 general purpose input/output (gpio) pins t hat may be used by the system designer as bit i/o ports. each g pio pin may be configured independently as an input or output through software c ontrol, and each gpio pin is shared with another on-chip fu nction. these alter- nate functions may be enabled via software or serial configuration eeprom. pin description the following tables lists the functions of the pins provided on the pes4t4. some of the functions listed may be multiplexed on to the same pin. the active polarity of a signal is defined using a suffix. signals ending with an ?n? are defined as being active, or asserted, whe n at a logic zero (low) level. all other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. signal type name/description pe0rp[0] pe0rn[0] i pci express port 0 serial data receive. differential pci express receive pair for port 0. pe0tp[0] pe0tn[0] o pci express port 0 serial data transmit. differential pci express trans- mit pair for port 0. pe2rp[0] pe2rn[0] i pci express port 2 serial data receive. differential pci express receive pair for port 2. pe2tp[0] pe2tn[0] o pci express port 2 serial data transmit. differential pci express trans- mit pair for port 2. pe3rp[0] pe3rn[0] i pci express port 3 serial data receive. differential pci express receive pair for port 3. pe3tp[0] pe3tn[0] o pci express port 3 serial data transmit. differential pci express trans- mit pair for port 3. pe4rp[0] pe4rn[0] i pci express port 4 serial data receive. differential pci express receive pair for port 4. pe4tp[0] pe4tn[0] o pci express port 4 serial data transmit. differential pci express trans- mit pair for port 4. perefclkp perefclkn i pci express reference clock. differential reference clock pair input. this clock is used as the reference clock by on-chip plls to generate the clocks required for the system logic and on-chip serdes. table 1 pci express interface pins signal type name/description msmbclk i/o master smbus clock. this bidirectional signal is used to synchronize transfers on the master smbus. msmbdat i/o master smbus data. this bidirectional signal is used for data on the mas- ter smbus. table 2 smbus interface pins
4 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information signal type name/description gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p2rstn alternate function pin type: output alternate function: reset output for downstream port 2 gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p4rstn alternate function pin type: output alternate function: reset output for downstream port 4 gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn0 alternate function pin type: input alternate function: i/o expander interrupt 0 input gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: gpen alternate function pin type: output alternate function: general purpose event (gpe) output gpio[9] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p3rstn alternate function pin type: output alternate function: reset output for downstream port 3 table 3 general purpose i/o pins signal type name/description apwrdisn i auxiliary power disable input. when this pin is active, it disables the device from using auxiliary power supply. cclkds i common clock downstream. the assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.this bit is used as the initial value of the slot clock configuration bit in all of the link status registers for downstream ports. the value may be override by modifying the sclk bit in the downstream port?s pcielsts register. cclkus i common clock upstream. the assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. this bit is used as the initial value of the slot clock configuration bit in the link status register for the upstream port. the value may be overridden by modifying the sclk bit in the pa_pcielsts register. perstn i fundamental reset. assertion of this signal resets all logic inside the pes4t4 and initiates a pci express fundamental reset. table 4 system pins (part 1 of 2)
5 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information rsthalt i reset halt. when this signal is asserted during a pci express fundamental reset, the pes4t4 executes the reset procedure and remains in a reset state with the master smbus active. this allows software to read and write registers internal to the device before normal device operation begins. the device exits the reset state when the rsthalt bit is cleared in the pa_swctl register by the smbus master. swmode[2:0] i switch mode. these configuration pins determine the pes4t4 switch operating mode. 0x0 - normal switch mode 0x1 - normal switch mode with serial eeprom initialization 0x2 - through 0xf reserved waken i/o wake input/output. the waken signal is an input or output. the waken signal input/output selection can be made through wakedir bit setting in the wakeupcntl register. signal type name/description jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic or jtag controller. jtag_tck is independent of the system clock with a nominal 50% duty cycle. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic or jtag controller. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic or jtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic and jtag tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board table 5 test pins signal type name/description v dd core i core vdd. power supply for core logic. v dd i/o i i/o vdd. lvttl i/o buffer power supply. v dd pe i pci express digital power. pci express digital power used by the digital power of the serdes. v dd ape i pci express analog power. pci express analog power used by the pll and bias generator. v tt pe i pci express termination power. v ss i ground. table 6 power and ground pins signal type name/description table 4 system pins (part 2 of 2)
6 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information pin characteristics note: some input pads of the pes4t4 do not contain internal pull- ups or pull-downs. unused inputs should be tied off to appropriate l evels. this is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. also, a ny input pin left floating can cause a slight in crease in power consumption. function pin name type buffer i/o type internal resistor notes pci express inter- face pe0rn[0] i cml serial link pe0rp[0] i pe0tn[0] o pe0tp[0] o pe2rn[0] i pe2rp[0] i pe2tn[0] o pe2tp[0] o pe3rn[0] i pe3rp[0] i pe3tn[0] o pe3tp[0] o pe4rn[0] i pe4rp[0] i pe4tn[0] o pe4tp[0] o perefclkn i lvpecl/ cml diff. clock input refer totable 8 perefclkp i smbus msmbclk i/o lvttl sti 1 1. schmitt trigger input (sti) . msmbdat i/o sti general purpose i/o gpio[9,7,2:0] i/o lvttl high drive pull-up system pins apwrdisn i lvttl input pull-down cclkds i pull-up cclkus i pull-up perstn i rsthalt i pull-down swmode[2:0] i pull-down waken i/o open-drain ejtag / jtag jtag_tck i lvttl sti pull-up jtag_tdi i sti pull-up jtag_tdo o jtag_tms i sti pull-up jtag_trst_n i sti pull-up table 7 pin characteristics
7 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information logic diagram ? pes4t4 figure 3 pes4t4 logic diagram reference clocks perefclkp perefclkn jtag_tck gpio[9,7,2:0] 5 general purpose i/o v dd core v dd i/o v dd pe v dd ape power/ground cclkus rsthalt system pins jtag_tdi jtag_tdo jtag_tms jtag_trst_n jtag pins v ss swmode[2:0] 3 cclkds perstn v tt pe pe0rp[0] pe0rn[0] pci express switch serdes input pe0tp[0] pe0tn[0] pci express switch serdes output port 0 port 0 pe2rp[0] pe2rn[0] pci express switch serdes input pe2tp[0] pe2tn[0] pci express switch serdes output port 2 port 2 pe3rp[0] pe3rn[0] pci express switch serdes input pe3tp[0] pe3tn[0] pci express switch serdes output port 3 port 3 pes4t4 pe4rp[0] pe4rn[0] pci express switch serdes input port 4 pe4tp[0] pe4tn[0] pci express switch serdes output port 4 msmbclk msmbdat master smbus interface waken apwrdisn
8 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information system clock parameters values based on systems running at recommended supply voltages and operating temperatures, as shown in tables 12 and 13. ac timing characteristics parameter description min typical max unit perefclk refclk freq input reference clock frequency range 100 125 1 1. the input clock frequency is 100 mhz. mhz refclk dc 2 2. clkin must be ac coupled. use 0.01 ? 0.1 f ceramic capacitors. duty cycle of input clock 40 50 60 % t r , t f rise/fall time of input clocks 0.2*rcui rcui 3 3. rcui (reference clock unit interval) refers to the reference clock period. v sw differential input voltage swing 4 4. ac coupling required. 0.6 1.6 v t jitter input clock jitter (cycle-to-cycle) 125 ps table 8 input clock requirements parameter description min typical max units pcie transmit t tx-rise , t tx-fall rise / fall time of txp, txn outputs 80 110 1 ps ui unit interval 399.88 400 400.12 ps t tx-max-jitter transmitter total jitter (peak-to-peak) 0.25 2 ui t tx-eye minimum tx eye width (1 - t tx-max-jitter )0.75 ui t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median 0.15 ui l tlat-10 transmitter data latency (for n=10) 9 11 bits l tlat-20 transmitter data latency (for n=20) 9 11 bits t tx-skew transmitter data skew between any 2 lanes 500 1300 ps t tx-idle-set-to- idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set 46ns t eiexit time to exit electrical idle (l0s) state into l0 12 16 ns t bten time from asserting beacon txen to beacon being trans- mitted on the lane 30 80 ns t rxdetecten pulse width of rxdetecten input 9.8 10 10.2 ns t rxdetect rxdetecten falling edge to rxdetect delay 1 2 ns pcie receive l rlat-10 recover data latency for n=10 28 29 bits l rlat-20 recover data latency for n=20 49 60 bits table 9 pcie ac timing characteristics (part 1 of 2)
9 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information figure 4 gpio ac timing waveform t rx-skew receiver data skew between any 2 lanes 20 ns t bddly beacon-activity on channel to detection of beacon 3 200 s t rx-idle_enter delay from detection of electrical idle condition on the channel to assertion of txidledetect output 10 20 ns t rx-idle_exit delay from detection of l0s to l0 transition to de-asser- tion of txidledetect output 510ns t rx-max-jitter receiver total jitter tolerance 0.65 ui t rx-eye minimum receiver eye width 0.35 ui t rx-eye-median-to- max jitter maximum time between jitter median and max deviation from median 0.325 ui 1. as measured between 20% and 80% points. will depend on package characteristics. 2. measured using pci express compliance pattern. 3. this is a function of beacon frequency. signal symbol reference edge min max unit timing diagram reference gpio gpio[9,7,2:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tpw_13b 2 2. the values for this symbol were determined by calculation, not by testing. none 50 ? ns see figure 4. table 10 gpio ac timing characteristics parameter description min typical max units table 9 pcie ac timing characteristics (part 2 of 2) tdo_13a tdo_13a tpw_13b extclk gpio (synchronous output) gpio (asynchronous input)
10 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information figure 5 jtag ac timing waveform signal symbol reference edge min max unit timing diagram reference jtag jtag_tck tper_16a none 25.0 50.0 ns see figure 5. thigh_16a, tlow_16a 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149.1, recommends that jtag_tms should be held at 1 while the signal applied at jtag_trst_n changes from 0 to 1. otherwise, a race may occur if jtag_trst_n is deasserted (going from low to high) on a rising edge of jtag _tck when jtag_tms is low, because the tap controller might go to either the run-test/idle state or stay in the test-logic-reset sta te. tsu_16b jtag_tck rising 2.4 ? ns thld_16b 1.0 ? ns jtag_tdo tdo_16c jtag_tck falling ? 11.3 ns tdz_16c 2 2. the values for this symbol were determined by calculation, not by testing. ? 11.3 ns jtag_trst_n tpw_16d 2 none 25.0 ? ns table 11 jtag ac timing characteristics tpw_16d tdz_16c tdo_16c thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms jtag_tdo jtag_trst_n
11 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information recommended operating supply voltages power-up/power-down sequence this section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper func tionality. for the pes4t4, the power-up sequence must be as follows: 1. v dd i/o ? 3.3v 2. v dd core, v dd pe, v dd ape ? 1.0v 3. v tt pe ? 1.5v when powering up, each voltage level must ramp and stabilize prio r to applying the next voltage in the sequence to ensure inter nal latch-up issues are avoided. there are no maximum time limitations in ramping to valid power levels. the power-down sequence must be in the reverse order of the power-up sequence. recommended operating temperature symbol parameter minimum typical maximum unit v dd core internal logic supply 0.9 1.0 1.1 v v dd i/o i/o supply except for serdes lvpecl/cml 3.135 3.3 3.465 v v dd pe pci express digital power 0.9 1.0 1.1 v v dd ape pci express analog power 0.9 1.0 1.1 v v tt pe pci express serial data transmit termination voltage 1.425 1.5 1.575 v v ss common ground 0 0 0 v table 12 pes4t4 operating voltages grade temperature commercial 0 c to +70 c ambient table 13 pes4t4 operating temperatures
12 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information power consumption parameter typ. max. unit conditions i dd i/o tbd tbd ma t ambient = 25 o c max. values use the maximum volt- ages listed in table 12. typical val- ues use the typical voltages listed in that table. i dd core normal mode tbd tbd ma standby mode 1 1. all ports in d1 state. tbd ? ma i dd pe, tbd tbd ma i dd ape tbd tbd ma i tt pe tbd tbd ma power dissipation normal mode tbd tbd w standby mode 1 tbd ? w table 14 pes4t4 power consumption
13 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information dc electrical characteristics values based on systems running at recommended supply voltages, as shown in table 12. note: see table 7, pin characteristics, for a complete i/o listing. i/o type parameter description min 1 typ 1 max 1 unit conditions serial link pcie transmit v tx-diffp-p differential peak-to-peak output voltage 800 1200 mv v tx-de-ratio de-emphasized differential output voltage -3 -4 db v tx-dc-cm dc common mode voltage -0.1 1 3.7 v v tx-cm-acp rms ac peak common mode output volt- age 20 mv v tx-cm-dc- active-idle-delta abs delta of dc common mode voltage between l0 and idle 100 mv v tx-cm-dc-line- delta abs delta of dc common mode voltage between d+ and d- 25 mv v tx-idle-diffp electrical idle diff peak output 20 mv v tx-rcv-detect voltage change during receiver detection 600 mv rl tx-diff transmitter differential return loss 12 db rl tx-cm transmitter common mode return loss 6 db z tx-deff-dc dc differential tx impedance 80 100 120 z ose single ended tx impedance 40 50 60 transmitter eye diagram tx eye height (de-emphasized bits) 505 650 mv transmitter eye diagram tx eye height (transition bits) 800 950 mv pcie receive v rx-diffp-p differential input voltage (peak-to-peak) 175 1200 mv v rx-cm-ac receiver common-mode voltage for ac coupling 150 mv rl rx-diff receiver differential return loss 15 db rl rx-cm receiver common mode return loss 6 db z rx-diff-dc differential input impedance (dc) 80 100 120 z rx-comm-dc single-ended input impedance 40 50 60 z rx-comm-high- z-dc powered down input common mode impedance (dc) 200k 350k v rx-idle-det- diffp-p electrical idle detect threshold 65 175 mv pcie refclk c in input capacitance 1.5 ? pf table 15 dc electrical characteristics (part 1 of 2)
14 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information other i/os low drive output i ol ?2.5?ma v ol = 0.4v i oh ?-5.5?ma v oh = 1.5v high drive output i ol ? 12.0 ? ma v ol = 0.4v i oh ?-20.0?ma v oh = 1.5v schmitt trig- ger input (sti) v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 v? input v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 v? capacitance c in ??8.5pf ? leakage inputs ? ? + 10 av dd i/o (max) i/o leak w / o pull-ups/downs ??+ 10 av dd i/o (max) i/o leak with pull-ups/downs ??+ 80 av dd i/o (max) 1. minimum, typical, and maximum values meet the requirements under pci specification 1.1. i/o type parameter description min 1 typ 1 max 1 unit conditions table 15 dc electrical characteristics (part 2 of 2)
15 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information package pinout ? 144-bga signal pinout for pes4t4 the following table lists the pin numbers and signal names for the pes4t4 device. pin function alt pin function alt pin function alt pin function alt a1 v ss c11 v dd core f9 v dd core j7 v ss a2 v dd i/o c12 v ss f10 v dd i/o j8 v dd core a3 apwrdisn d1 jtag_tdo f11 v dd i/o j9 v ss a4 v tt pe d2 msmbclk f12 gpio_01 1 j10 v ss a5 v tt pe d3 v dd core g1 v ss j11 v dd i/o a6 pe0tp00 d4 v ss g2 jtag_trst_n j12 gpio_09 1 a7 v dd pe d5 v ss g3 v ss k1 v ss a8 pe0rp00 d6 v ss g4 v dd core k2 v dd core a9 v dd i/o d7 v dd core g5 v ss k3 v dd i/o a10 swmode_0 d8 v ss g6 v dd core k4 v dd core a11 swmode_1 d9 v ss g7 v ss k5 v dd pe a12 v ss d10 v ss g8 v dd core k6 v ss b1 v dd core d11 perstn g9 v ss k7 v dd pe b2 waken d12 rsthalt g10 v dd core k8 v ss b3 cclkus e1 jtag_tdi g11 v ss k9 v dd core b4 v dd pe e2 msmbdat g12 gpio_02 1 k10 v dd i/o b5 v dd pe e3 v dd i/o h1 perefclkp k11 v ss b6 pe0tn00 e4 v dd core h2 v dd i/o k12 v ss b7 v dd pe e5 v ss h3 v dd ape l1 pe2rn00 b8 pe0rn00 e6 v dd core h4 v ss l2 v ss b9 cclkds e7 v ss h5 v ss l3 pe2tp00 b10 swmode_2 e8 v ss h6 v ss l4 v ss b11 v ss e9 v ss h7 v dd core l5 pe3tn00 b12 v ss e10 v dd core h8 v ss l6 v dd ape c1 jtag_tms e11 v ss h9 v ss l7 pe3rn00 c2 v ss e12 gpio_00 1 h10 v dd core l8 v tt pe c3 v ss f1 jtag_tck h11 v ss l9 pe4rp00 c4 v dd core f2 v dd i/o h12 gpio_07 1 l10 v ss c5 v dd ape f3 v dd core j1 perefclkn l11 pe4tn00 c6 v dd ape f4 v ss j2 v ss l12 v dd core c7 v ss f5 v dd core j3 v ss m1 pe2rp00 c8 v dd core f6 v ss j4 v ss m2 v ss c9 v dd core f7 v dd core j5 v ss m3 pe2tn00 c10 v ss f8 v ss j6 v dd core m4 v tt pe table 16 pes4t4 144-pin signal pin-out (part 1 of 2)
16 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information alternate signal functions power pins m5 pe3tp00 m7 pe3rp00 m9 pe4rn00 m11 pe4tp00 m6 v ss m8 v dd ape m10 v ss m12 v ss pin gpio alternate e12 gpio_00 p2rstn f12 gpio_01 p4rstn g12 gpio_02 ioexpintn0 h12 gpio_07 gpen j12 gpio_09 p3rstn table 17 pes4t4 alternate signal functions v dd core v dd core v dd i/o v dd pe v dd ape v tt pe b1 f9 a2 a7 c5 a4 c4 g4 a9 b4 c6 a5 c8 g6 e3 b5 h3 l8 c9 g8 f2 b7 l6 m4 c11 g10 f10 k5 m8 d3 h7 f11 k7 d7 h10 h2 e4 j6 j11 e6 j8 k3 e10 k2 k10 f3 k4 f5 k9 f7 l12 table 18 pes4t4 power pins pin function alt pin function alt pin function alt pin function alt table 16 pes4t4 144-pin signal pin-out (part 2 of 2)
17 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information ground pins signals listed alphabetically v ss v ss v ss v ss a1 d10 g11 k1 a12 e5 h4 k6 b11 e7 h5 k8 b12e8h6k11 c2 e9 h8 k12 c3 e11 h9 l2 c7 f4 h11 l4 c10 f6 j2 l10 c12 f8 j3 m2 d4 g1 j4 m6 d5 g3 j5 m10 d6 g5 j7 m12 d8 g7 j9 d9 g9 j10 table 19 pes4t4 ground pins signal name i/o type location signal category apwrdisn i a3 system cclkds i b9 cclkus i b3 gpio_00 i/o e12 general purpose input/output gpio_01 i/o f12 gpio_02 i/o g12 gpio_07 i/o h12 gpio_09 i/o j12 jtag_tck i f1 jtag jtag_tdi i e1 jtag_tdo i d1 jtag-tms o c1 jtag-trst_n i g2 msmbclk i/o d2 smbus msmbdat i/o e2 table 20 89pes4t4 alphabetical signal list (part 1 of 2)
18 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information pe0rn00 i b8 pci express pe0rp00 i a8 pe0tn00 o b6 pe0tp00 o a6 pe2rn00 i l1 pe2rp00 i m1 pe2tn00 o m3 pe2tp00 o l3 pe3rn00 i l7 pe3rp00 i m7 pe3tn00 o l5 pe3tp00 o m5 pe4rn00 i m9 pe4rp00 i l9 pe4tn00 o l11 pe4tp00 o m11 perefclkn i j1 perefclkp i h1 perstn i d11 system rsthalt i d12 system swmode_0 i a10 swmode_1 i a11 swmode_2 i b10 waken i/o b2 v dd core, v dd ape, v dd i/o, v dd pe , v tt pe see table 18 for a listing of power pins. v ss see table 19 for a listing of ground pins. signal name i/o type location signal category table 20 89pes4t4 alphabetical signal list (part 2 of 2)
19 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information pes4t4 pinout ? top view 123456 7 89101112 vss (ground) v dd core (power) v dd i/o (power) v tt pe (power) v dd pe (power) v dd ape (power) signals a b c d e f g h j k l m x a b c d e f g h j k l m 123456 7 89101112 x x x x
20 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information pes4t4 package drawing ? 144-pin bc144/bcg144
21 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information pes4t4 package drawing ? page two
22 of 23 september 7, 2007 idt 89hpes4t4 data sheet advance information revision history august 16, 2007 : initial publication of advanced data sheet. september 7, 2007 : added power-up/power down sequence.
23 of 23 september 7, 2007 idt 89hpes4t4 data sheet corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com advance information for tech support: email: ssdhelp@idt.com phone: 408-284-8208 ? ordering information valid combinations 89HPES4T4ZABC 144-pin bc144 package, commercial temperature 89HPES4T4ZABCg 144-pin green bc144 package, commercial temperature nn aaaa nnan aa a operating voltage device family product package temp range h blank commercial temperature (0c to +70c ambient) product family 89 serial switching product bc144 144-ball cabga bc 4t4 4-lane, 4-port 1.0v +/- 0.1v core voltage detail pci express switch pes legend a = alpha character n = numeric character bcg144 144-ball cabga, green bcg aa device revision za za revision

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